{"product_id":"9783642118012","title":"Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation : 19th International Workshop, PATMOS 2009, The Netherlands, Revised Selected Papers (Lecture Notes in Computer Science) \u003cVol. 5953\u003e","description":"\u003cp\u003e§16§This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability 〓04§Keynotes.- Robust Low Power Embedded SRAM Design: From System to Memory Cell.- Variability in Advanced Nanometer Technologies: Challenges and Solutions.- Subthreshold Circuit Design for Ultra-Low-Power Applications.- Special Session.- SystemC AMS Extensions: New Language - New Methods - New Applications.- Session 1: Variability 〓04§nagement.- Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip.- Data-Driven Clock Gating for Digital Filters.- Power Management and Its Impact on Power Supply Noise.- Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems.- Session 3: Low Power Circuits 〓04§ion Analysis in Chip Multiprocessors.- Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform.- BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation.- Session 4: Power 〓04§omplex Logic Gates.- A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).- Routing Resistance Influence in Loading Effect on Leakage Analysis.- Session 7: Low Power Design Studies.- Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks.- An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.- Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t  Domain By Architectural Folding.- A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.\u003c\/p\u003e","brand":"Springer","offers":[{"title":"Default Title","offer_id":49169733714147,"sku":"00000_00000_00000_00000","price":54.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0764\/3758\/6147\/files\/9783642118012-1.jpg?v=1788434200","url":"https:\/\/usa.kinokuniya.com\/products\/9783642118012","provider":"Books Kinokuniya USA","version":"1.0","type":"link"}